In contrast, 8-bitters need multiple instructions to handle 16-bit addresses.
#IAR 8051 PRICE CODE#
It seems that the 16-bit ISA hits somehow the “sweet spot” for the best code density, perhaps because the addresses are also 16-bit wide and are handled in a single instruction. Interestingly, the winner is MSP430, which is a 16-bit architecture. I believe that this code is quite representative to typical projects that run on these small MCUs. QF-nano contains an event queue, a timer module, and a simple event loop. The QEP-nano consists mostly of a conditional logic to execute hierarchical state machines. The code consists of a small hierarchical state machine processor (called QEP-nano), and a tiny framework (called QF-nano).
To support the point, I present below a table that shows the code size of a tiny state machine framework written in C (called QP-nano), which has been compiled for a dozen or so very different single-chip MCUs. The deciding factor is how old a design is, whereas the newer instruction set architectures (ISAs) generally far outperform the older ISAs. From my experience with several single-chip MCUs I draw a different conclusion: the CPU size (8-, 16-, 32-bits) almost doesn’t matter for the code density.
This becomes obvious when one looks at the silicon die of any MCU, which is completely dominated by the ROM and RAM blocks, the CPU being almost insignificant somewhere in the corner.īut, I would disagree with Jack’s statement that “tiny (8-bit) processors make more efficient use of memory”. I also agree that the most deciding factor for the price of a single-chip microcontroller (MCU) is the efficiency of its memory use, in other words, the code density. The recent Jack Ganssle’s “Breakpoints” blog on makes an excellent point that the same forces (the Moore’s law), which drive down the prices of high-end processors open even more market opportunities at the low-end of the price spectrum.
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